Loop Pipelining and Optimization for Run Time Reconnguration ?

Lack of automatic mapping techniques is a signiicant hurdle in obtaining high performance for general purpose computing on recon-gurable hardware. In this paper, we develop techniques for mapping loop computations from applications onto high performance pipelined conng-urations. Loop statements with generalized directed acyclic graph dependencies are mapped onto multiple pipeline segments. Each pipeline segment is executed for a xed number of iterations before the hardware is reconngured at runtime to execute the next segment. The reconnguration cost is amortized over the multiple iterations of the execution of the loop statements. This alleviates the bottleneck of high reconnguration overheads in current architectures. The paper describes heuristic techniques to construct pipeline conngurations which have reduced total execution time including the runtime reconnguration overheads. The performance beneets which can be achieved using our approach are illustrated by mapping example application loop onto Virtex series FPGA from Xilinx.